There have been conventionally known various techniques for obtaining an output signal that is obtained by adjusting the phase of a signal. For example, there has been known DLL (Delay Locked Loop) as one technique for obtaining an output signal that is obtained by adjusting the phase of a signal. DLL includes, for example, a delay element that adds a delay amount to a phase. The DLL compares the phase of an input signal and a value that is obtained by adding the delay amount of the delay element to the phase of the input signal, and generates a delay signal of which the phase is delayed as an output signal.
In addition, there is disclosed a technique for providing an offset control circuit (resistance dividing circuit) to adjust the phase of an output signal as one technique for obtaining an output signal that is obtained by adjusting the phase of a signal.    Patent Document 1: Japanese Laid-open Patent Publication No. 61-225905    Patent Document 2: Japanese Laid-open Patent Publication No. 7-67333
However, there is a problem in that the above conventional technique cannot adjust the phase of an output signal in fine detail.
For example, in the conventional technique, each delay element adds a delay amount, which is not less than a predetermined minimum value and is not more than a predetermined maximum value, to the phase of an input signal. In this case, a predetermined minimum value is the propagation delay time of the delay element and indicates phase resolution between delay elements. For this reason, in the conventional technique, because a delay amount that is added to the phase of an input signal cannot be less than or equal to a predetermined minimum value, the phase of an output signal cannot be adjusted not more than a predetermined minimum value in fine detail. In addition, Patent Document 1 and Patent Document 2 do not disclose a technique for adjusting the phase of an output signal in fine detail.